Cypress FM4 Series - ALE Timing Register 0 to 7 (ATIM0 to ATIM7)

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 819
6.4 ALE Timing Register 0 to 7 (ATIM0 to ATIM7)
The ATIM0 to ATIM7 registers set the automatic wait time of MALE.
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial value
-
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
Reserved
ALEW
ALES
ALC
Attribute
-
R/W
R/W
R/W
Initial value
-
0100
0101
1111
[bit31:12]Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit11:8] ALEW: Address Latch Enable Width
These bits are used to set the assertion period for MALE.
MALE signal will be asserted during (ALEW+1) cycle.
bit11
bit10
bit9
bit8
Description
0
0
0
0
1 cycle
...
...
0
1
0
0
5 cycles [Initial value]
...
...
1
1
1
1
16 cycles
[bit7:4] ALES: Address Latch Enable Setup cycle
These bits are used to set the setup cycle for ALE assertion.
ALE will not be asserted from the access start during (ALES) cycle.
bit7
bit6
bit5
bit4
Description
0
0
0
0
0 cycle
...
...
0
1
0
1
5 cycles [Initial value]
...
...
1
1
1
1
15 cycles
[bit3:0] ALC : Address Latch Cycle
These bits are used to set the address latch cycle.
Address will be output from CS assert and data line during (ALC+1) cycle.
bit3
bit2
bit1
bit0
Description
0
0
0
0
1 cycle
…
…
1
1
1
1
16 cycles [Initial value]
Note:
− Setups to the ATIM register is available only in multiplex mode.