Cypress FM4 Series - Bus Block Diagram

CHAPTER 1: System Overview
26 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1.1 Bus Block Diagram
Figure 1-1 illustrates the bus block diagram.
Figure 1-1 Bus Block Diagram
Cortex -M4F
TM
Core
FLASH
I/F
FLASH
(Main)
ROM table
ETM/HTM
TPIU/ETB
AHB bus matrix
SWJ-DP
SRAM0
DMAC
SRAM1
I-Code bus
D-Code bus
System bus
AHB to AHB
bridge
USB ch.0
AHB
Peripherals
AHB to APB
bridge
AHB to APB
bridge
APB1
Peripherals
EXT-bus
I/F
AHB to
APB bridge
APB0
Peripherals
APB2
Peripherals
APB1
APB2
APB0
SD-Card I/F
Ethernet-
MAC
AHB to AHB
bridge
FLASH I/F
FLASH
(Work/Dual)
Ethernet/SD-Card/GDC bus
DMAC bus
FPU
SRAM2
DSTC
DSTC bus
USB ch.1
EXT-bus
AHB bridge
MPU
High-Speed
Quad-SPI
Quad-SPI
AHB bridge
GDC
Note:
− There are some areas to which no DMA transfer can be performed. For details, see the Access
other than CPU column in Table 1-1.