Cypress FM4 Series - Operations in Standby Modes

CHAPTER 6: Low Power Consumption Mode
202 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3. Operations in Standby Modes
This section explains the operations in standby modes.
There are four types of standby mode: Sleep mode (high speed CR sleep mode, main sleep mode, PLL
sleep mode, low speed CR sleep mode and sub sleep mode), Timer mode (high speed CR timer mode,
main timer mode, PLL timer mode, low speed CR timer mode and sub timer mode), RTC mode and
STOP mode.
Clock Operation States in Standby Mode
The table below shows the respective states of the oscillator clocks, CPU clock, AHB bus clock and APB
bus clocks in Sleep mode, Timer mode, RTC mode and Stop mode.
Table 3-1 Clock Operation States in Sleep Mode
Sleep Mode
High Speed CR
Sleep Mode
Main Sleep
Mode
PLL Sleep Mode
Low Speed CR
Sleep Mode
Sub Sleep Mode
High speed CR clock
Operating
Stopped
Main clock
The state changes
according to the
setting of the MOSCE
bit.
Operating
The state changes
according to the
setting of the MOSCE
bit and the PINC bit.
Stopped
Main PLL clock
The state changes according to the
setting of the MOSCE bit and the PLLE
bit.
Operating
Stopped
Low speed CR clock
Operating
Sub clock
The state changes according to the setting of the SOSCE bit.
Operating
USB PLL clock
The state changes
according to the
setting of the MOSCE
bit and the UPLLEN
bit.
The state changes according to the setting
of the UPLLEN bit.
Stopped
I
2
S PLL clock
The state changes
according to the
setting of the MOSCE
bit and the IPLLEN
bit.
The state changes according to the setting
of the IPLLEN bit.
Stopped
GDC PLL clock
The state changes
according to the
setting of the MOSCE
bit, GPINC
*1
and the
GPLLEN
*1
bit.
The state changes according to the setting
of the GPINC
*1
and the GPLLEN
*1
bit.
Stopped
CPU clock
Stopped
AHB bus clock
High speed CR clock
Main clock
PLL clock
Low speed CR clock
Sub clock
APB0 bus clock
High speed CR clock
Main clock
PLL clock
Low speed CR clock
Sub clock
APB1 bus clock
High speed CR clock
Main clock
PLL clock
Low speed CR clock
Sub clock
* The APBC1EN bit enables or disables the APB1 bus clock.
APB2 bus clock
High speed CR clock
Main clock
PLL clock
Low speed CR clock
Sub clock
* The APBC2EN bit enables or disables the APB2 bus clock.
*1: For details of the GPINC bit and GPLLEN bit, refer to GDC Part.