Cypress FM4 Series - Page 201

CHAPTER 6: Low Power Consumption Mode
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 201
MOSCE: MOSCE bit in System Clock Mode Control Register (SCM_CTL)
SOSCE: SOSCE bit in System Clock Mode Control Register (SCM_CTL)
PLLE: PLLE bit in System Clock Mode Control Register (SCM_CTL)
RCS: RSC bit in System Clock Mode Control Register (SCM_CTL)
MORDY: MORDY bit in System Clock Mode Status Register (SCM_STR)
SORDY: SORDY bit in System Clock Mode Status Register (SCM_STR)
PLRDY: PLRDY bit in System Clock Mode Status Register (SCM_STR)
PINC: PINC bit in PLL Clock Stabilization Wait Time Setup Register (PSW_TMR)
*: For details of the SCM_CTL, SCM_STR and PSW_TMR registers, see Chapter Clock.
Note:
− The CPU automatically secures a voltage stabilization wait time (a few hundred µs) for the
operation mode transition of the built-in regulator immediately before returning from low speed
CR timer mode, sub timer mode, RTC mode, stop mode, deep standby RTC mode or deep
standby stop mode. After the voltage stabilization wait time has lapsed, the CPU returns to a Run
mode.