Cypress FM4 Series - Debug Break Watchdog Timer Control Register (DBWDT_CTL)

CHAPTER 2-1: Clock
72 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.13 Debug Break Watchdog Timer Control Register (DBWDT_CTL)
The DBWDT_CTL sets the watchdog timer count operation for debug mode tool break.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
DPHWBE
Reserved
DPSWBE
Reserved
Attribute
R/W
-
R/W
-
Initial value
0
-
0
-
Register functions
[bit7] DPHWBE: HW-WDG debug mode break bit
bit
Description
0
HW-WDG stops counting at the tool break [Initial value]
1
HW-WDG continues counting at the tool break
[bit6] Reserved: Reserved bit
0 is read from this bit.
Set this bit to 0 when writing.
[bit5] DPSWBE: SW-WDG debug mode break bit
bit
Description
0
SW-WDG stops counting at the tool break [Initial value]
1
SW-WDG continues counting at the tool break
[bit4:0] Reserved: Reserved bits
0b00000 is read from these bits.
Set these bits to 0b00000 when writing.
Note:
− This register is not initialized by software reset.