Cypress FM4 Series - Clock Control Register

CHAPTER 15: SD Card Interface
858 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
2.14 Clock Control Register
At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select bits
according to the setting of the Capabilities Register.
D15 D08
D07 D06
D05
D04 D03
D02
D01
D00
SDCLK Frequency Select
Upper Bits of SDCLK
Frequency Select
Clock Generator Select
Rsvd
SD Clock Enable
Internal Clock Stable
Internal Clock Enable
Bit
Attribute
Description
02
RW
SD Clock Enable
This bit controls the output of the SD Clock.
After 0 has been written to this bit, a period lasting for a total of 3 bus clock cycles and 2 SD
Clock cycles elapses before the SD clock stops.
When enabling the SD clock by changing the setting of this bit from 0 to 1, take account of
the period mentioned above.
1: Enable
0: Disable
Set/Reset
Condition
Set
1 Write
Reset ("0")
System reset
Software Reset For All
0 Write
01
ROC
Internal Clock Stable
The Host Driver cannot write a value to the SD Clock Enable bit until this bit is set to 1.
1: Ready
0: Non Ready
Set/Reset
Condition
Set
The Internal Clock Enable bit is 1 and the Internal Clock
becomes stable.
Reset ("0")
System reset
Software Reset For All
Other than Set condition 1), Reset condition 1) and Reset
condition 2)
00
RW
Internal Clock Enable
To control the SD card interface, set this bit to 1 before starting the internal clock.
1: Oscillate
0: Stop
Set/Reset
Condition
Set
1 Write
Reset ("0")
System reset
Software Reset For All
0 Write
For details of other bits in this register, refer to SD Specifications Part A2.