Cypress FM4 Series - USB Ch.0 Odd Packet Size DMA Enable Register (ODDPKS)

CHAPTER 8: Interrupts
432 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.40 USB ch.0 Odd Packet Size DMA Enable Register (ODDPKS)
If data is transferred in the IN direction in USB ch.0 automatic transfer in which the DMAC is used, only in
the last data in the last packet, the effective bit width is compulsorily converted into 1 byte (8 bits) before
the data is written to a USB endpoint.
Register configuration
bit
31
8
Field
Reserved
Attribute
R
Initial value
0x000000
bit
7
6
5
4
3
2
1
0
Field
Reserved
ODDPKS
Attribute
R
R/W
Initial value
000
00000
Register function
[bit31:5] Reserved: Reserved bits
Write 0 to a reserved bit. A reserved bit reads 0.
[bit4] ODDPKS4
Value
Description
0
There is no conversion of the bit width for DMA transfer by the DMAC.
1
If the transfer destination address in the DMAC is USB.EP5DT, the bit width of the last
transfer data is converted into one byte.
[bit3] ODDPKS3
Value
Description
0
There is no conversion of the bit width for DMA transfer by the DMAC.
1
If the transfer destination address in the DMAC is USB.EP4DT, the bit width of the last
transfer data is converted into one byte.
[bit2] ODDPKS2
Value
Description
0
There is no conversion of the bit width for DMA transfer by the DMAC.
1
If the transfer destination address in the DMAC is USB.EP3DT, the bit width of the last
transfer data is converted into one byte.
[bit1] ODDPKS1
Value
Description
0
There is no conversion of the bit width for the DMA transfer by the DMAC.
1
If the transfer destination address in the DMAC is USB.EP2DT, the bit width of the last
transfer data is converted into one byte.