Cypress FM4 Series - Software-Burst Transfer

CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 463
3.2 Software-Burst Transfer
This section explains Software-Burst transfer.
Figure 3-2 shows an example of the operation of Software-Burst transfer. In this example, the following
settings apply.
− Transfer mode: Software request Burst transfer (ST=1, IS[5:0]=000000,
MS=01)
− Transfer source start address: SA(DMACSA=SA)
− Transfer source address: Fixed, reload available (FS=1, RS=1)
− Transfer destination start address: DA(DMACDA=DA)
− Transfer destination address: Increment and reload not available (FD=0, RD=0)
− Transfer data size: Word (32 bits), the number of blocks =3, the number of
transfers =2 (TW=10, BC=2, TC=1)
− Reload of the number of transfers: Number of transfers to be reloaded (RC=1)
Figure 3-2 Example of Operation of Software-Burst Transfer
CPU
Start request
DMAC
End report
SA+0
SA+0
SA+0
SA+0
SA+0
SA+0
DA+0
DA+4
DA+8
DA+12
DA+16
DA+20
BC+1
TC+1
BC+1
DMAC performs the following operation, when the transfer content is set from CPU and then the start of
the transfer is instructed.
− Due to the specification of the transfer data width, each transfer is performed by word (32bits).
− According to the start addresses of the transfer source and transfer destination, the data width and
the incremented/fixed specification, the transfer is performed in the area from the address SA to
address DA, for the number of blocks (=BC+1). As the transfer source address is specified to be
fixed, it is the same as the transfer source start address (SA+0).
− In the case of Burst transfer, the transfer is executed continuously without generating Transfer
Gaps.
− DMAC performs data transfer for the number of blocks (=BC+1) by the number of transfers (=TC+1).
The size of data to be transferred by each transfer request from CPU is "Data width (TW) Number
of blocks (BC+1) Number of transfers (TC+1)".
− When the transfer is completed, DMAC notifies CPU of the completion.
In the case of Burst transfer, no Transfer Gap is generated, unlike the Block transfer. As the channel to be
controlled takes the possession of the system bus access right, it can be used to put the priority on that
particular channel.