CHAPTER 10: DMAC
462 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
DMAC performs the following operation, when the transfer content is set from CPU and then the start of
the transfer is instructed.
− Due to the specification of the transfer data width, each transfer is performed by half-word (16bits).
− According to the start addresses of the transfer source and transfer destination, the data width and
the incremented/fixed specification, the transfer is performed in the area from the address SA to
address DA, for the number of blocks (=BC+1).
− In the case of Block transfer, a Transfer Gap occurs every time transfer of one block is completed.
− DMAC performs data transfer for the number of blocks (=BC+1) by the number of transfers (=TC+1).
The size of data to be transferred by each transfer request from CPU is "Data width (TW) ×
Number of blocks (BC+1) × Number of transfers (TC+1)".
− Once the transfer is completed, DMAC notifies CPU of the completion.
− If the start of transfer is instructed again after the completion of the transfer, the transfer is restarted
from the previous transfer start address (SA+0), because the transfer source address has been set
to be reloaded (RS=1). As the transfer destination address has not been specified to be reloaded
(RD=0), the transfer is started from the next address (DA+12) after the previous transfer end
address. Also, as the reload of BC/TC has been specified, the same values as for the previous
transfer are reloaded for the number of blocks and the number of transfers for the next transfer.
Transfer Gap is a time period during which no transfer is performed, and it is inserted to prevent one of
the DMAC channels from taking the possession of the system bus access right. If multiple channels have
transfer requests, DMAC switches the channels that will perform the transfer operation at the timing of the
Transfer Gap. The frequency of Transfer Gap generation can be controlled by adjusting the settings of BC
and TC.
Moreover, the bus access right is also passed on to CPU at the Transfer Gap timing. System buses in this
product are in Multi-layered configuration with a special system bus dedicated to DMA. For this reason, if
there is no conflict between CPU and the destination of access, transfer can be performed at the same
time as the CPU operation. Even if there is a conflict between CPU and the destination of access, the
CPU operation is little affected, as long as the DMAC transfer is in a different address area group (RAM
and Peripheral, or Flash memory and RAM, etc.). However, if the transfer is in the same address area
group (RAM and RAM, etc.), the CPU operation and/or system performance may be affected, depending
on the number of blocks used; therefore, attention must be paid.
("Address area group" mentioned above refers to a group of address areas that are connected on the
AHB system bus with the same bus bridge.)
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