Cypress FM4 Series - Timing Register 0 to Timing Register 7 (TIM0 to TIM7)

CHAPTER 14: External Bus Interface
812 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.2 Timing Register 0 to Timing Register 7 (TIM0 to TIM7)
The TIM0 to TIM7 registers set the auto wait time at SRAM/Flash memory access.
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
WIDLC
WWEC
WADC
WACC
Attribute
R/W
R/W
R/W
R/W
Initial value
0000
0101
0101
1111
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
RIDLC
FRADC
RADC
RACC
Attribute
R/W
R/W
R/W
R/W
Initial value
1111
0000
0000
1111
[bit31:28] WIDLC: Write Idle Cycle
These bits set the number of idle cycles after write access.
Write idle cycle will be used during (WIDLC+1) cycle.
bit31
bit30
bit29
bit28
Description
0
0
0
0
1 cycle [Initial value]
...
...
1
1
1
1
16 cycles
[bit27:24] WWEC: Write Enable Cycle
These bits set the number of assert cycles of write enable.
Write enable will be asserted during (WWEC+1) cycle.
The setting of these bits affects the byte mask signal (MDQM).
bit27
bit26
bit25
bit24
Description
0
0
0
0
1 cycle
...
...
0
1
0
1
6 cycles [Initial value]
...
...
1
1
1
0
15 cycles
1
1
1
1
Setting is prohibited.