Cypress FM4 Series - Page 813

CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 813
[bit23:20] WADC: Write Address Setup cycle
These bits set the number of setup cycles of write address.
Write address setup will be used during (WADC+1) cycle.
The address is output during the cycle set by these bits, but a write enable signal is not asserted until the
set cycle starts.
bit23
bit22
bit21
bit20
Description
0
0
0
0
1 cycle
...
...
0
1
0
1
6 cycles [Initial value]
...
...
1
1
1
0
15 cycles
1
1
1
1
Setting is prohibited.
[bit19:16] WACC: Write Access Cycle
These bits set the number of cycles required for write access.
Write access cycle will be used during (WACC+1) cycle.
The address remains unchanged during the cycle set by these bits.
The number of cycles set by these bits must be equal to or more than the sum of the address setup cycle
(WADC) and the write enable cycle (WWEC).
bit19
bit18
bit17
bit16
Description
0
0
0
0
Setting is prohibited.
0
0
0
1
Setting is prohibited.
0
0
1
0
3 cycles
...
...
1
1
1
1
16 cycles [Initial value]
[bit15:12] RIDLC: Read Idle Cycle
These bits set the number of idle cycles after read access.
Read access cycle will be used during (RIDLC+1) cycle.
They are used to avoid data collision caused by a write access occurring immediately after a read access.
bit15
bit14
bit13
bit12
Description
0
0
0
0
1 cycle
...
...
1
1
1
1
16 cycles [Initial value]