Cypress FM4 Series - Page 814

CHAPTER 14: External Bus Interface
814 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
[bit11:8] FRADC: First Read Address Cycle
The functions of these bits are changed by the settings of MODE:PAGE (Page read access setting) and
MOEXEUP (MOEX width setting method selection).
− When MODE:PAGE=0 (Page read access: OFF) and MOEXEUP=0
These bits do not affect the settings of Page read access and MPEX width.
− When MODE:PAGE=0 (Page read access OFF) and MOEXEUP=1
These bits set the MOEX width. In this case, a setup with RACC ≥ RADC+FRDC is required.
bit11
bit10
bit9
bit8
Description
0
0
0
0
1 cycle [Initial value]
...
...
1
1
1
1
16 cycles
− When MODE:PAGE=1 (Page read access: ON) and MOEXEUP=0
These bits set the waiting time at initial access at the page read access of Flash memory. Before
setting values other than 0 to these bits, SET 0 to RADC (Read Access Setup Cycle).
bit11
bit10
bit9
bit8
Description
0
0
0
0
0 cycle [Initial value]
...
...
1
1
1
1
15 cycles
− When MODE:PAGE=1(Page read access: ON) and MOEXEUP=1
This setting is prohibited.
[bit7:4] RADC: Read Address Setup cycle
These bits set the number of setup cycles of read address.
Read address setup cycle will be used during (RADC) cycle.
Within the read address setup cycle, MCSX and address are asserted but MOEX is not asserted. If 0 is
set to any of these bits, MOEX and MCSX are always asserted.
The set value must be less than the number of read access cycles. (RADC < RACC).
When using NOR Flash memory page access mode, set these bits to 0b0000.
If the access size is more than the target width, or if a device such as NAND Flash memory needs to
switch HIGH and LOW of read enable (MOEX or MNREX), set these bits to 0b0001 or a higher value.
bit7
bit6
bit5
bit4
Description
0
0
0
0
0 cycles [Initial value]
...
...
1
1
1
1
15 cycles