Cypress FM4 Series - APB0 Prescaler Register (APBC0_PSR)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 63
5.4 APB0 Prescaler Register (APBC0_PSR)
The APBC0_PSR sets the APB0 bus clock frequency division.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
APBC0
Attribute
-
R/W
Initial value
-
00
Register functions
[bit7:2] Reserved: Reserved bits
0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit1:0] APBC0: APB0 bus clock frequency division setting bits
bit1
bit0
Description
0
0
1/1 [Initial value]
0
1
1/2
1
0
1/4
1
1
1/8
Note:
− This register is not initialized by software reset.