CHAPTER 7-2: VBAT Domain(A)
290 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
7.8 Port Function Set Register (VBPFR)
VBPFR Register selects the usage of pins.
The interface circuit type for this register is type 3.
[bit7:6] Reserved: Reserved bits
These bits read 0b00.
In a write access to these bits, write 0b00 to them.
[bit5:4] SPSR1, SPSR0: Oscillation pin function set bits
The P46 and P47 pins are used as digital (GPIO) pins.
The P46 and P47 pins are used as 32 kHz oscillation pins. [Initial value]
The P46 and P47 pins are used as digital (GPIO) pins.
The P46 pin is used as an external clock input pin.
The P47 pin is used as a digital (GPIO) pin.
[bit3] VPFR3: Port function of P46/X0A pin set bit
[bit2] VPFR2: Port function of P47/X1A pin set bit
A read access reads the value of this bit.
The pin corresponding to the VPFR3 bit or to the VPFR2 bit is used as a GPIO port.
The pin corresponding to the VPFR3 bit or to the VPFR2 bit is used as an I/O pin of a peripheral
function. (Initial value)
[bit1] VPFR1: Port function of P49/VWAKEUP pin set bit
[bit0] VPFR0: Port function of P48/VREGCTL pin set bit
A read access reads the value of this bit.
The pin corresponding to the VPFR1/VPFR0 bit is used as a GPIO port. [Initial value]
The pin corresponding to the VPFR1/VPFR0 bit is used as an I/O pin of a peripheral function.