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Cypress FM4 Series - Register Map

Cypress FM4 Series
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A. Register Map
958 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
1. Register Map
Register map is shown on the table every module/function.
[How to read the each table]
Clock/Reset Base_Address : 0x4001_0000
Base_Address
Register
+ Address
+3
+2
+1
+0
0x000
-
-
-
SCM_CTL[B,H,W]
00000-0-
0x004
-
-
-
SCM_STR[B,H,W]
00000-0-
0x008
STB_CTL[B,H,W]
00000000 00000000 -------- ---0--00
0x00C
-
-
RST_STR[B,H,W]
-------0 00000-01
Notes:
The register table is represented in the little-endian.
When performing a data access, the addresses should be as below according to the access size.
Word access: Address should be multiples of 4 (least significant 2 bits should be 0x00)
Half word access: Address should be multiples of 2 (least significant bit should be 0x0)
Byte access: -
Do not access the test register area.
Do not access the area that is not written in the register table.
When the register is accessed by larger unit than register size, for the reserved area to
access at the same time, the read value is undefined, and writing is invalid.
Initial value after reset
"1": Initial value is 1
"0": Initial value is 0
"X": Initial value is undefined
" - ": Reserved bit
Register name
Access unit
(B : byte, H : half word, W : word)
Rightmost register address (For word-length access, the "+0" column of the register is
the LSB of the data.)
- : Reserved area
* : Test register area
Module/function name and its base address

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