CHAPTER 14: External Bus Interface
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 827
6.8 SDRAM Timing Register (SDTIM)
The SDTIM register set the automatic wait time at SDRAM access.
[bit31] BOFF: Buffer readout bit
This bit sets buffer for SDRAM during read.
Buffer for SDRAM during read is enabled. [Initial Value]
Buffer for SDRAM during read is disabled.
Notes:
− Set this bit when SDON=0 of the SDRAM mode register.
− This bit exists for TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products. It does not exist for
TYPE1-M4 products.
[bit30:26] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit25:24] TDPL: Data-in to Precharge Lead Time
These bits set the latency from write to precharge.
[bit23:20] TREFC: Refresh Cycle time
These bits set the latency for a command following the refresh operation.
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