Cypress FM4 Series - RTC Mode Control Register (PMD_CTL)

CHAPTER 6: Low Power Consumption Mode
232 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
8.3 RTC Mode Control Register (PMD_CTL)
The RTC Mode Control Register selects whether the CPU transits to either RTC mode or Stop mode, or
to either deep standby RTC mode or deep standby stop mode.
Bit
7
6
5
4
3
2
1
0
Field
Reserved
RTCE
Attribute
-
R/W
Initial value
0000000
0
[bit7:1] Reserved: Reserved bits
These bits always read 0b0000000.
Writing a value to these bits has no effect on operation.
[bit0] RTCE: RTC mode control bit
This bit selects whether the CPU transits to Stop mode, deep standby stop mode, or to RTC mode, deep
standby RTC mode.
Bit
Description
0
Stop mode or deep standby stop mode [initial value]
1
RTC mode or deep standby RTC mode
Standby mode is selected when DSTM bit is 0 and deep standby mode is selected when DSTM bit is 1.
Notes:
− This register is not initialized by the software reset or the deep standby transition reset.
− Writing 1 to the RTCE bit is effective only if the SORDY bit in the System Clock Mode Status
Register (SCM_STR) is 1.
− If the RTCE bit is 1, the sub oscillator is enabled, regardless of the setting of the SOSCE bit in the
System Clock Mode Control Register (SCM_CTL) and that of the SORDY bit in the System Clock
Mode Status Register (SCM_STR).