Cypress FM4 Series - PLL Clock Stabilization Wait Time Setup Register (PSW_TMR)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 69
5.10 PLL Clock Stabilization Wait Time Setup Register (PSW_TMR)
The PSW_TMR sets the main PLL clock stabilization wait time.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
Reserved
PINC
Reserved
POWT
Attribute
-
R/W
-
R/W
Initial value
-
0
-
000
Register functions
[bit7:5] Reserved: Reserved bits
0b000 is read from these bits.
Set these bits to 0b000 when writing.
[bit4] PINC: PLL input clock select bit
bit
Description
0
Selects CLKMO (main clock oscillation) [Initial value]
1
Selects CLKHC (high-speed CR clock)
Note: Setting this bit to 1 has some restrictions.
See 1. Notes when high-speed CR is used for the master clock in B. List of Notes of Appendixes.
[bit3] Reserved: Reserved bit
0 is read from this bit.
Set this bit to 0 when writing.
[bit2:0] POWT: Main PLL clock stabilization wait time setup bits
bit2
bit1
bit0
Description
0
0
0
2
9
/ FCRH : Approx. 128 µs * [Initial value]
0
0
1
2
10
/ FCRH : Approx. 256 μs *
0
1
0
2
11
/ FCRH : Approx. 512 μs *
0
1
1
2
12
/ FCRH : Approx. 1.02 ms *
1
0
0
2
13
/ FCRH : Approx. 2.05 ms *
1
0
1
2
14
/ FCRH : Approx. 4.10 ms *
1
1
0
2
15
/ FCRH : Approx. 8.20 ms *
1
1
1
2
16
/ FCRH : Approx. 16.40 ms *
*: When FCRH=4 MHz
Notes:
− Set each oscillation stabilization wait time before enabling the PLL oscillation enable bit (PLLE) of
the SCM_CTL.
If you change POWT bit while waiting for oscillation stability of the PLL oscillator, the oscillation
stabilization wait time is not guaranteed.
− This register is not initialized by software reset.