CHAPTER 8: Interrupts
436 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5. Usage Precautions
Note the following when using the interrupt controller.
− The interrupt controller is notified of the interrupt request signals from peripheral functions in terms
of level. When exiting the processing of an interrupt, always clear the interrupt request for that
interrupt.
− When other interruption with a high priority is processing, the interrupt request from peripheral
functions notified to NVIC is pended inside NVIC. When canceling the interrupt request which was
pended inside NVIC, clear the interrupt request from peripheral functions, and clear the interrupt
request which was pended inside NVIC by the Interrupt Clear-Pending Registers (addresses:
0xE000E280 to 0xE000E29C) installed in the NVIC.
− The NMIX pin is shared with a general-purpose port. After a reset is released, the initial function of
the pin is general-purpose port, and NMI input is masked. To use the NMI function, enable the NMI
function using the port setting. For details, see Chapter External Interrupt and NMI Controller.
− If the DMA transfer by the DSTC is used, the transfer end interrupt (HWINT[n]) from the DSTC is
generated instead of the interrupt from a peripheral function. Due to the above configuration, the
NVIC makes an interrupt from a peripheral function, and a transfer end interrupt from the DSTC
jump to the same interrupt vector. Use the DREQENB[n] Register to select the interrupt to be
processed.
However, for some peripheral functions (I2S, HS-SPICNT, CAN-FD and programmable CRC)
handling interrupts and transfer requests to DSTC separately, the DREQENB register setting of
DSTC determines whether the DMA transfer is performed or not. In this case, interrupts from
peripheral functions and transfer completion interrupts from DSTC are input to NVIC respectively.
− For the relationship between specific event detection registers and interrupt enable registers in a
peripheral function, see the chapter on that peripheral function.
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