Cypress FM4 Series - Operations in Sleep Modes (High Speed CR Sleep Mode, Main Sleep Mode, PLL Sleep Mode, Low Speed CR Sleep Mode, Sub Sleep Mode)

CHAPTER 6: Low Power Consumption Mode
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 205
3.1 Operations in Sleep Modes (High-Speed CR Sleep Mode, Main Sleep
Mode, PLL Sleep Mode, Low-Speed CR Sleep Mode, Sub Sleep Mode)
Sleep mode is classified as a standby mode. In Sleep mode, the CPU clock stops and, in turn, power
consumption is reduced.
Functions of Sleep Mode
 CPU and on-chip memory
In Sleep mode, the clock being supplied to the CPU stops. The AHB bus clock continues operating. The
on-chip memory continues operating and retains data.
 Peripherals
The APB0 bus clock runs even in Sleep mode. The APB1 bus clock is enabled or disabled by the
APBC1EN bit and the APB2 bus clock by the APBC2EN bit. Peripherals operate in their respective states
set at the transition to Sleep mode.
 Watch counter and RTC
The watch counter and the RTC are not affected by Sleep mode. They continue operating according to
the settings set prior to transition to Sleep mode.
 Oscillator clocks
Table 3-1 shows the status of each oscillator clock.
 Resets and interrupts
Resets and interrupts can be used for returning from Sleep mode.
 External bus
The external bus is still active in Sleep mode.
 Pin state
All pin settings are held in Sleep mode.
Procedure for Setting Sleep Mode
Execute the following procedure to make the CPU transit to Sleep mode.
1. Write 0 to the SLEEPDEEP bit in the Cortex-M4F System Control Register.
2. Execute the WFI instruction or the WFE instruction.
The CPU transits to a Sleep mode corresponding to the current clock mode indicated in the RCM[2:0]
bits in the System Clock Mode Status Register (SCM_STR).
For details of the System Clock Mode Control Register (SCM_CTL), see Chapter Clock.