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Cypress FM4 Series - Port Input Data Register (Pdirx)

Cypress FM4 Series
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CHAPTER 12: I/O Port
602 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
4.4 Port Input Data Register (PDIRx)
The PDIRx register indicates input data of a pin.
List of PDIR Register Configuration
bit
31
16
15
0
Initial value
Attribute
Corresponding port
Reserved
PDIR0
0x0000
R
P0F to P00
Reserved
PDIR1
0x0000
R
P1F to P10
Reserved
PDIR2
0x0000
R
P2F to P20
Reserved
PDIR3
0x0000
R
P3F to P30
Reserved
PDIR4
0x0000
R
P4F to P40
Reserved
PDIR5
0x0000
R
P5F to P50
Reserved
PDIR6
0x0000
R
P6F to P60
Reserved
PDIR7
0x0000
R
P7F to P70
Reserved
PDIR8
0x0000
R
P8F to P80
Reserved
PDIR9
0x0000
R
P9F to P90
Reserved
PDIRA
0x0000
R
PAF to PA0
Reserved
PDIRB
0x0000
R
PBF to PB0
Reserved
PDIRC
0x0000
R
PCF to PC0
Reserved
PDIRD
0x0000
R
PDF to PD0
Reserved
PDIRE
0x0000
R
PEF to PE0
Reserved
PDIRF
0x0000
R
PFF to PF0
Detailed Register Configuration
bit
31
16
15
0
Field
Reserved
PDIRx
Register Function
[bit31:16] Reserved: Reserved bits
0x0000 is read out from these bits.
When writing these bits, set them to 0x0000.
[bit15:0] PDIRx: Port Input Data Register x
Reads out input data of a pin.
bit
Description
Reading
0
Regardless of pin function settings (PFR/EPFR/DDR/PDOR), it indicates that a pin is in the
status of L level input or L level output. When a special pin is selected by ADE/SPSR, as input
is cut off, 0 is always read out.
1
Regardless of pin function settings (PFR/EPFR/DDR/PDOR), it indicates that a pin is in the
status of H level input or H level output.
Writing
Writing does not affect anything.

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