Cypress FM4 Series - Operation Flows of DSTC; SW Transfer Flow

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 531
3.3 Operation Flows of DSTC
This section explains the operation of the DSTC with flow charts.
3.3.1 SW Transfer Flow
The operations the DSTC executes after receiving an SW Start Trigger from the CPU are explained below.
Figure 3-8 shows a flow chart of the operations of the DSTC. Numbers in the figure correspond to those
used in the explanation after the figure.
Figure 3-8 DSTC Operation Flow (SW Transfer)
#4
Running HW[n] transfer ?
Y
#9
HW[n] transfer
error end?
Y
#5
SW priority > HW priority?
by CFG:SWPR
#6
Is there HW
transfer request?
N Y
Y N
N
Y
#12
(CFG:ESTE==0)?
N
#1 Start SW transfer (SWTR register write from CPU )
#14
MONERS <= HW[n] error information
DQMSK[n] <= 1
MONERS:ESTOP <=1
#13
MONERS <= HW[n] error information
DQMSK[n] <= 1
#24
MONERS <= SW error information
SWTR:SWREQ <= 0
MONERS:ESTOP <= 1
#16
Data transfer
by DES @SWDESP
#8 Waiting until HW[n]
transfer chaining timing
#17 Update DESP for chain
SWTR.SWDESP <= next
#20 SWTR:SWREQ <=0
#3 SWTR:SWREQ <=1
SWTR:SWST <=0
SWTR:SWDESP <= val.
#7 Start next HW transfer
#11
HW[n] transfer
chain lock?
Y N
#22
(CFG:ESTE==0)?
Y
N
#10
HW[n] transfer
chain?
N
Y
N
(A)
(A)
#25
SW transfer error end
(Wait next trigger)
(A)
Please see Figure 3-10.
#21
SW transfer normal end
(Wait next trigger)
#23
MONERS <= SW error information
SWTR:SWREQ <= 0
#15
(MONERS:ESTOP==1)?
(A)
Y
N
Transfer normal end
without I.F. set
Chain start trigger
#18
(CHLK==1)?
#19 SWTR:SWREQ <=0
SWTR:SWST <=1
#2 (SWTR:SREQ==0)
&& (MONERS:ESTOP==0)
&&(CMD==00) ?
Y
N
N
Y
#26
Write access ignored end
Branch
Transfer error end
Out of Infinity loop end
Transfer normal end
with I.F. set
(C)
(C)
(B)
(B)