CHAPTER 11: DSTC
532 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
#1 Start the SW Start transfer from a write access to the SWTR Register from the CPU.
#2 If the SWTR Register, the MONERS Register and the CMD Register are
(SWTR:SWREQ==0)&&(MONERS:ESTOP==0)&&(CMD==00), the DSTC proceeds to #3. Otherwise
the DSTC proceeds to #26.
#3 Set "1" to SWTR:SWREQ and clear SWTR:SWST to 0. Store the specified value in SWTR:SWDESP.
Processes explained in #4 to #15 are details of operations of Arbiter 2 and processes in other HW
Transfer.
#4 If other HW Transfer is being executed, the DSTC proceeds to #8. Otherwise the DSTC proceeds to #5.
#5 Determine whether the SW Transfer or the HW Transfer has higher priority according to the setting of
the SWPR bit in the CFG Register. If the SW Transfer has higher priority, the DSTC proceeds to #16.
Otherwise the DSTC proceeds to #6.
#6 If there is other HW Transfer request, the DSTC proceeds to #7. Otherwise the DSTC proceeds to #16.
#7 Start data transfer for that HW Transfer.
#8 Until that HW Transfer has completed the DES, the DSTC keeps waiting for the start of the execution
of the SW Transfer which is issued in #1.
#9 If that HW Transfer has ended in the form of error, the DSTC proceeds to #12. Otherwise the DSTC
proceeds to #10.
#10 If there is a Chain Start transfer in that HW Transfer, the DSTC proceeds to #11. Otherwise the DSTC
proceeds to #5.
#11 If the Chain Start transfer in that HW Transfer is locked, the DSTC proceeds to #7. Otherwise the
DSTC proceeds to #5.
#12 If CFG:ESTE is 0, the DSTC proceeds to #13. Otherwise the DSTC proceeds to #14.
#13 If there has been no error record (EST[2:0] = 000) in the MONERS Register, the MONERS Register
records the error information of the DES of the HW Transfer that has caused an error. If there is an
error record (EST[2:0] ≠ 000), the DSTC sets the DER bit to 1. The DSTC proceeds to #5.
#14 The same process as #13 is executed. At the same time, the ESTOP bit in the MONERS Register is
set to 1. The DSTC proceeds to #15.
#15 The DSTC is holding the start of the execution of the SW Transfer which is issued in #1 while the
ESTOP bit is 1. If an ERCLR command is issued by the CPU to the CMD Register and the ESTOP bit
is cleared to 0, the DSTC proceeds to #5.
#16 The flow inside the bold box shows the transfer operations of the DSTC according to the DES
specified in DESP. For details of the flow inside the bold box, see section Operation Flow after
Specifying of DESP. In the case of the SW Start transfer, the DSTC executes the transfer according to
the DES specified in SWDESP. After the transfer has been processed, the operation of the DSTC
branches to one of the five operations shown in Figure 3-10.
#17 In the case of a Chain Start, the DSTC updates the value of SWTR:SWDESP.
#18 If CHLK is 1, the DSTC proceeds to #16 and successively executes the transfers started by the
Chain Start. Otherwise the DSTC proceeds to #5.
#19 If the transfer ends normally and there is an interrupt flag set instruction, the DSTC executes the
processes in #19. The DSTC clears SWTR:SWREQ to 0 and sets SWTR:SWST to 1.
#20 If the transfer ends normally and there is no interrupt flag set instruction, the DSTC executes the
processes in #20. The DSTC clears SWTR:SWREQ to 0.
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