CHAPTER 1: System Overview
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 35
2.1 Option Configuration
Table 2-1 shows the option configuration of this family for Cortex-M4 core.
For detail of feature, see Cortex-M4 Technical Reference Manual.
Table 2-1 Option configuration
Memory Protection Unit (MPU)
Flash Patch and Breakpoint Unit (FPB)
Data Watchpoint and Trace Unit (DWT)
Instrumentation Trace Macrocell Unit (ITM)
Embedded Trace Macrocell (ETM)
Advanced High-performance Bus Access
Port (AHB-AP)
AHB Trace Macrocell (HTM) interface and
Embedded Trace Buffer (ETB)
Trace Port Interface Unit (TPIU)
Wake-up Interrupt Controller (WIC)
Debug Port AHB-AP interface
Floating-Point Unit (FPU)
Interrupt priority levels
Number of watchpoint comparators
Number of breakpoint comparators
Instruction: 6
Literal: 2
Instruction: 6
Literal: 2
Instruction: 6
Literal: 2
Instruction: 6
Literal: 2
*: Some products do not have this function. For details, see Block Diagram in Data Sheet of the product
used.
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