CHAPTER 1: System Overview
32 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
2. Cortex-M4F Architecture
This section explains the core architecture used in this family.
Cortex-M4F core block architecture* used in this family is as follows:
− Cortex-M4 Core
− NVIC
− FPU
− DWT
− ITM
− FPB
− MPU
− ETM
− HTM
− SWJ-DP
− TPIU
− ETB
− ROM Table
*: The architecture varies depending on the products. For details, see 2.1 Option Configuration.
Cortex-M4 Core
High-performance 32-bit processor core (Arm Cortex-M4 core) is equipped with this family.
This peripheral manual does not describe the details of Cortex-M4 core.
For the details, see “Cortex-M4 Technical Reference Manual”.
− Cortex-M4 Core Version
For the version of Cortex-M4 core, see Data Sheet of the product used.
NVIC (Nested Vectored Interrupt Controller)
For this family, one NMI (non-maskable interrupt) and maximum 128 peripheral interrupts (IRQ0 to
IRQ127)*1 can be used.
Also, interrupt priority register (from 0xE000E400) is comprised of 4 bits, and 16 interrupt priority levels
can be configured.
For the details of peripheral interrupts, see the chapter of the target “Interrupts” after check the product
currently used with Configuration of interrupts, and for NMI operations, see also another chapter External
Interrupt and NMI Control Block.
NMI pin is assigned for a combined use with a general-purpose port. Its initial value after a reset release
is set to the general-purpose port, and NMI input is masked.
When NMI is used, enable NMI in the port setting.
For the details, see another chapter I/O Port.
* 1: Cortex-M4 Technical Reference Manual defines an exception type: IRQ as an external interrupt.
In this peripheral manual, to distinguish from an interrupt by an external pin External Interrupt and
NMI Control Block, the exception type: IRQ is indicated as a peripheral interrupt.
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