CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 87
3. Peripheral Clock Gating Control
This section explains the control of the peripheral clock gating.
The register of the peripheral clock gating becomes an initial state by bus reset (PRESET2)*. Be sure to
execute the clock control for necessary peripheral functions immediately after reset of the bus because
the bus reset (PRESET2) is generated by all reset factors.
*: For the generating condition of bus reset (PRESET2), see Chapter Reset.
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