Cypress FM4 Series - Transfer Source Address Register (DMACSA)

CHAPTER 10: DMAC
500 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.5 Transfer Source Address Register (DMACSA)
This section explains transfer source address register (DMACSA).
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
DMACSA[31:16]
Attribute
R/W
Initial Value
0x0000
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
DMACSA[15:0]
Attribute
R/W
Initial Value
0x0000
[bit31:0] DMACSA[31:0] : DMAC Source Address
These bits specify the transfer start address of the transfer source.
It is not possible to set unaligned address to transfer data width (TW[1:0]). The value of these bits can be
read during the transfer.
In the case of DMACB:FS=1, the transfer source address is set to a fixed value and no change occurs.
In the cases of DMACB:FS=0 and DMACB:RS=0, the value is incremented according to TW[1:0].
Upon successful transfer completion, it is the next address after the transfer completion address.
Upon unsuccessful transfer completion, it is the value set during the suspension.
In the cases of DMACB:FS=0 and DMACB:RS=1, it is incremented according to TW[1:0] during the
transfer. Upon completion of the transfer, the value set when the transfer started is reloaded.
bit31:0
Function
Specifies the transfer source address from which the transfer starts.
(Initial value: 0x00000000)