CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 395
4.9 IRQ019/020/096/097 Batch Read Register (IRQxxxMON)
The IRQ019MON, IRQ020MON, IRQ096MON and IRQ097MON Registers can read out at once the
interrupts (QPRC ch.0 to ch.3, GDC) assigned to exception no. 35, no. 36, no. 112 and no. 113
respectively.
Register configuration
Register function
[bit31:9] Reserved: Reserved bits
A reserved bit reads 0.
[bit8] GDCINT
Register by has the following features. Other than the following becomes a reserved bit “0” is read.
There is no interrupt request of the GDC SafetyStream0.
An interrupt request of the GDC SafetyStream0 has been made.
There is no interrupt request of the GDC DisplayStream0.
An interrupt request of the GDC DisplayStream0 has been made.
[bit7:6] Reserved: Reserved bits
A reserved bit reads 0.