Cypress FM4 Series - Operations in Timer Modes (High Speed CR Timer Mode, Main Timer Mode, PLL Timer Mode, Low Speed CR Timer Mode, Sub Timer Mode)

CHAPTER 6: Low Power Consumption Mode
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 207
3.2 Operations in Timer Modes (High-Speed CR Timer Mode, Main Timer
Mode, PLL Timer Mode, Low-Speed CR Timer Mode, Sub Timer Mode)
In Timer mode, the base clock supply stops. Since the stop of the base clock supply causes the CPU
clock, the AHB bus clock and all APB bus clocks to stop, power consumption is further reduced. In this
mode, all functions stop operating except for the following: all oscillators, PLL, hardware watchdog timer,
watch counter, RTC, clock failure detector and Low Voltage Detection Circuit.
Functions of Timer Mode
 CPU and on-chip memory
In Timer mode, the CPU clock supplied to the CPU, and the AHB bus clock supplied to the on-chip
memory and the DMA controller stop. However, data in the on-chip memory is retained. In addition, the
debug function stops.
 Peripherals
In Timer mode, all APB bus clocks stop. Except for the hardware watchdog timer, the watch counter, the
RTC and the clock supervisor, all resources stop at their respective states they were in immediately
before the CPU transits to Timer mode.
 Watch counter and RTC
The watch counter and the RTC are not affected by Timer mode. They continue operating according to
the settings set prior to transition to Timer mode.
 Oscillator clocks
Table 3-2 shows the status of each oscillator clock.
 Resets and interrupts
Resets and interrupts can be used for returning from Timer mode.
 External bus
The external bus stops in Timer mode.
 Pin state
The SPL bit in the Standby Mode Control Register (STB_CTL) can control whether an external pin stays
at the state it was in immediately before the CPU transits to Timer mode or changes to high impedance
state.
Procedure for Setting Timer Mode
Execute the following procedure to make the CPU transit to Timer mode.
1. Write 0 to the RTCE bit in the RTC Mode Control Register (PMD_CTL).
2. Write 0x1ACC, 0 and 0b00 to the KEY bits, DTSM bit and STM bits in the Standby Mode Control
Register (STB_CTL) respectively. Set the state of each pin in Timer mode by using the SPL bit.
3. Write 1 to the SLEEPDEEP bit in the Cortex-M4F System Control Register.
4. Execute the WFI instruction or the WFE instruction.
The CPU transits to a TIMER mode corresponding to the current clock mode indicated in the RCM[2:0]
bits in the System Clock Mode Status Register (SCM_STR).