Cypress FM4 Series - DMAC DMA Request Selection Register (DRQSEL)

CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 385
4.1 DMAC DMA Request Selection Register (DRQSEL)
The DMA Request Selection Register (DRQSEL) enables using an interrupt signal from a peripheral
function as a transfer request to the DMAC. Such interrupt signal can be transferred through the DMA
transfer by the DMAC.
Register configuration
bit
31
0
Field
DRQSEL[31:0]
Attribute
R/W
Initial value
0x00000000
Register function
[bit31:0] DRQSEL[31:0]
The connection in the SEL1 selector in Figure 2-1 changes according to the setting of a bit in the
DRQSEL Register. If the setting of a bit is 1, an interrupt signal is connected to the SEL1 selector as a
transfer request signal to the DMAC. If the setting of a bit is 0, an interrupt signal is connected to the
SEL1 selector as an interrupt signal to the NVIC or as a transfer request signal to the DSTC.
Bit
Corresponding interrupt signal name
31
External pin interrupt ch.3
30
External pin interrupt ch.2
29
External pin interrupt ch.1
28
External pin interrupt ch.0
27
MFS ch.7 transmission interrupt
26
MFS ch.7 reception interrupt
25
MFS ch.6 transmission interrupt
24
MFS ch.6 reception interrupt
23
MFS ch.5 transmission interrupt
22
MFS ch.5 reception interrupt
21
MFS ch.4 transmission interrupt
20
MFS ch.4 reception interrupt
19
MFS ch.3 transmission interrupt
18
MFS ch.3 reception interrupt
17
MFS ch.2 transmission interrupt
16
MFS ch.2 reception interrupt
15
MFS ch.1 transmission interrupt
14
MFS ch.1 reception interrupt
13
MFS ch.0 transmission interrupt
12
MFS ch.0 reception interrupt
11
Base timer ch.6 source 0 (IRQ0) interrupt
10
Base timer ch.4 source 0 (IRQ0) interrupt
9
Base timer ch.2 source 0 (IRQ0) interrupt
8
Base timer ch.0 source 0 (IRQ0) interrupt
7
A/D converter unit 2 scan conversion interrupt
6
A/D converter unit 1 scan conversion interrupt
5
A/D converter unit 0 scan conversion interrupt
4
USB ch.0 function endpoint 5 DRQ interrupt
3
USB ch.0 function endpoint 4 DRQ interrupt
2
USB ch.0 function endpoint 3 DRQ interrupt
1
USB ch.0 function endpoint 2 DRQ interrupt
0
USB ch.0 function endpoint 1 DRQ interrupt