CHAPTER 19: Programmable CRC
938 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.2 Control Flow for the Programmable CRC (during Input Data DMA
Transfer with DSTC)
Figure 3-2 shows a flowchart of the control method when transferring input data with HW startup DMA
transfer of DSTC to acquire the CRC computing result. The numbers shown in the figure correspond the
numbers of the following descriptions.
Figure 3-2 Flowchart of the Control for the Programmable CRC during Input Data Transfer with DSTC
#1 Start controlling for input data transfer with HW startup transfer of DSTC.
#2 and #3 Check that LOCK of the PRGCRC_CFG register is "0" and go to the next step.
#4 Initialize the programmable CRC. Set appropriate initial values to the PRGCRC_POLY register, the
PRGCRC_SEED register and the PRGCRC_FXOR register. The PRGCRC_SEED register always
performs a single writing with 32-bit width access (word access).
#5 Initialize DSTC. Set an appropriate value for the control register and descriptor of DSTC. The
DREQENB[n] register sets to "1" the register of the channel number to which the transfer request is
connected from the programmable CRC. DES0.MODE="1" and DES0.DMSET="1" are required to be
set. For transfer source address, specify the memory area where the input data is stored. For transfer
destination address, specify the PRGCRC_WR register.
#6 Set the PRGCRC_CFG register. In this example, the data transfer control with DSTC is performed
without using interrupts. Set CIEN="0". Always set "100000" for TEST. Set an appropriate value for
data output format. Set CDEN="1". By writing access of CDEN="1", DMA the transfer request signal
from the programmable CRC is asserted and the input data transfer by DSTC is started.
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