Cypress FM4 Series - Error Status Clear Register (ESCLR)

CHAPTER 14: External Bus Interface
838 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.14 Error Status Clear Register (ESCLR)
The ESCLR register initializes the error status register (EST) and write error address register (WEAD).
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial Value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial Value
-
bit
15
14
13
12
11
10
9
8
Field
Reserved
Attribute
-
Initial Value
-
bit
7
6
5
4
3
2
1
0
Field
Reserved
WERRCLR
Attribute
-
W
Initial
-
1
[bit31:1] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit0] WERRCLR: Write Error Clear
By writing 0 to this bit, the Error Status Register (EST) and Write Error Address Register (WEAD) are
cleared to the initial state. bit0 is not changed to 0 by writing this bit. 0 is always read.