Cypress FM4 Series - Peripheral Clock Gating Function Usage Precautions

CHAPTER 2-2: Clock Gating
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 109
5. Peripheral Clock Gating Function Usage Precautions
This section explains the precautions for using peripheral clock gating functions by peripheral function.
Overview
 Control of a peripheral function to which a clock supply is stopped
The register access to a peripheral function to which a clock supply is stopped, both read and write, is not
guaranteed. The read value is undefined, and the write operation is prohibited.
The internal state can be reset by controlling peripheral function reset control register 0 to 2 (MRST0,
MRST1, and MRST2) while the peripheral clock is gated.
 Combination of peripheral clock settings
Be sure to set all the target peripheral functions to the clock supply side by the peripheral clock control
registers 0 to 2 (CKEN0, CKEN1, and CKEN2) for the functions operated by combining two or more
peripheral functions. For example, set a relevant unit of the A/D converter used and a relevant channel of
the base timer to the clock supply side respectively by the peripheral clock control registers (CKEN0 and
CKEN1) when the base timer is selected for use by the timer trigger of the A/D converter.
 Initialization conditions of peripheral clock settings
The peripheral clock gating function is initialized by the following reset. After issuing the following reset,
be sure to reconfigure the peripheral clock gating function.
For details of the following resets, see Chapter Resets.
− Power-on reset (PONR)
− Low voltage detection reset (LVDH)
− INITX pin input(INITX)
− Software watchdog reset (SWDGR)
− Hardware watchdog reset (HWDGR)
− Clock failure detection reset (CSVR)
− Anomalous frequency detection reset (FCSR)
− Software reset (SRST)
− APB2 bus reset (APBC2_PSR)
− Deep standby transition reset (DSTR)
Multi-Function Serial Interface
 LIN Sync field detection: LSYN
Execute the setting of the operation clock supply to the corresponding multi-function timer (input capture)
separately with the setting of the peripheral clock of multi-function serial interface when the input capture
(ICU) is used in the LIN bus interface mode. For the connection between the multi-function serial
interface and the input capture, see Extended Pin Function Setting Register (EPFR) in Chapter of I/O
port.
 MFS I
2
S interface
Execute the setting of the operation clock supply to the corresponding MFS I
2
S separately with the setting
of the peripheral clock of multi-function serial interface when the I
2
S is used in the clock synchronous
serial interface mode (CSIO).