CHAPTER 2-2: Clock Gating
110 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
Base Timer
Clock setting unit of base timer
The peripheral clock control of the base timer is executed in the unit of four channels described in Table
5-1.
Table 5-1 Correspondence between Peripheral Clock Gating Setting and Base Timer Channels
Setting Bit of Peripheral Clock Control
Register (CKEN1)
Base Timer ch3, ch2, ch1, ch0
Base Timer ch7, ch6, ch5, ch4
Base Timer ch11, ch10, ch9, ch8
Base Timer ch15, ch14, ch13, ch12
Multi-function Timer
FRT Selection register
For using the following FRT selection function, set the operation clock of the multi-function timer unit on
which source-side FRT is mounted to the supply side.
− OCU Connection FRT selection register (OCFS)
− ICU Connection FRT selection register (ICFS)
− ADC Start-up compare connection FRT selection register (ADCMP)
PPG
Clock Control of PPG
The control of input clock to PPG synchronizes with the settings of input clock to the multi-function timer.
For PPG channel numbers and unit numbers of multi-function timer, see Table 5-2.
Table 5-2 Multi-function Timer and PPG Input Clock Control
Unit Number of Multi-function Timer
External Bus Interface
Individual reset control of external bus interface
When the external bus interface is individually reset with bit26 (EXBRST) of the peripheral function reset
control register 0 (MRST0), the setting of the register in the external bus interface is not initialized though
its operation stops.
USB (Function/Host)
Clock control target
The gating and supplying of the clock for the USB communication cannot be controlled with USBCK bit of
the peripheral clock control register 2 (CKEN2). Execute the control of the clock for the USB
communication with UCEN bit of USB clock control register (UCCR) or USB/Ethernet clock control
register (UCCR). For details, see USB Clock Generation in FM4 Family Peripheral Manual
Communication Macro Part.
To Next Page
Loading...
