Cypress FM4 Series - DMAC Operation and Control Procedure for Hardware (EM=0) Transfer

CHAPTER 10: DMAC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 477
4.3 DMAC Operation and Control Procedure for Hardware (EM=0) Transfer
This section explains DMAC operation and control procedure for hardware (EM=0) transfer.
Figure 4-5 Transitional Diagram of Hardware (EM=0) Transfer State
Figure 4-5 shows a transitional diagram of the states of the channel to be controlled for hardware (EM=0)
transfer. The numbers next to the transitional lines in the figure correspond to the numbers which appear
in the following control procedures. The solid transitional lines indicate transitions of state instructed by
CPU, while the broken transitional lines indicate transitions of state due to DMAC/Peripheral operation.
Some parts of the explanation below state "See the software transfer procedure". This means that where
the same control as in the software transfer procedure applies, no special mentioning is required;
therefore, such redundant explanation has been omitted. In this example, the explanation assumes that
EM=0 is set.
Transition by CPU
Transition by DMAC/Peripheral
2
5
,
6
,
7
4
Disable
DE=0 or EB=0 or
DH!=0000 or PB=1
initial : SS=000
after stop : SS=code
Transfer
DE=1 EB=1
DH=0000 PB=0
SS=000
Pause
8
8
1
,
9
,
1
3
Reset
1
0
1
1
1
2
Wait 1st trigger
DE=1 EB=1
DH=0000 PB=0
SS=000
3
1
3
DE=1 EB=1
DH!=0000 or PB=1
SS=111