CHAPTER 10: DMAC
476 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
A certain channel is performing transfer operation. CPU issues an instruction to put individual-channel
operation on pause to that channel. The instruction is issued after the transfer is completed and it moves
to Disable state (DE=1, DH=0000, EB=0, PB=0). This phenomenon can occur, because the channel
currently performing transfer operation changes its state outside CPU’s intention. In this case, the bit
values of the relevant channel change to (DE=1, DH=0000, EB=1, PB=1) due to instruction from CPU,
but SS[2:0] remains 101, the value set upon the completion. If the operation is stopped by a pause
instruction, SS[2:0] will be 111; therefore, it will be possible to distinguish between the pause state and the
state in which the transfer has been completed. It should be noted that if an instruction to cancel the
pause is issued without checking the state of the channel by SS[2:0], a new transfer will accidentally start,
as shown in Figure 4-4.
− Additional Matter 1
As ST is cleared upon the completion of a transfer, the read value of ST is 0 after the completion
of the transfer. In the case of software transfer, it should be noted that 1 must always be written to
ST, regardless of its read value.
− Additional Matter 2
An instruction to enable individual-channel operation cannot be issued during the period after the
previous instruction to enable individual-channel operation instructs the start of transfer and
before the completion of the transfer is confirmed. This is because the channel to be controlled
may change its state outside CPU’s intention and an instruction to start a new transfer may be
issued when DMAC has moved to Disable state (EB=0). Even if the SS[2:0] value confirms that
the channel to be controlled is in Transfer state, the channel to be controlled may move to Disable
state during the period between that point and the write operation.
− Additional Matter 3
The DE and DH values can only be rewritten from CPU and these registers are never cleared
from DMAC. Therefore, there is no problem to write DE=1 and DH=0000 during the transfer
operation.
DH is not cleared, if an instruction to disable individual-channel operation is issued to a channel in
all-channel Pause state (DE=1, DH!=0000, EB=1, PB=0). After the instruction, the relevant
channel moves to Disable state (DE=1, DH!=0000, EB=0, PB=0). To start a new transfer of the
relevant channel, write DE=1 and DH=0000. This indicates that the cancellation of the pause of
all-channel operation is required in order to start a new transfer of the individual channel.
− Additional Matter 4
The SS[2:0] value is set from DMAC upon the completion of a transfer and it is never rewritten
from DMAC as long as it is in Disable state. Even if the SS[2:0] value is not cleared, the next
transfer can be started. However, if it moves to Transfer state, the SS[2:0] value may be cleared
from DMAC (or may not be cleared). When an interrupt from DMAC is used, it should be noted
that the interrupt signal is deasserted at a timing which is not intended by CPU, if it moves to
Transfer state without clearing SS[2:0].
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