Cypress FM4 Series - SDRAM Command Register (SDCMD)

CHAPTER 14: External Bus Interface
830 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.9 SDRAM Command Register (SDCMD)
The SDCMD register outputs the set value to the external pin for controlling SDRAM.
bit
31
30
29
28
27
26
25
24
Field
PEND
Reserved
Attribute
R
-
Initial Value
0
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
SDCKE
SDCS
SDRAS
SDCAS
SDWE
Attribute
-
R/W
R/W
R/W
R/W
R/W
Initial Value
-
0
0
0
0
0
bit
15
14
13
12
11
10
9
8
Field
SDAD[15:8]
Attribute
R/W
Initial Value
0x00
bit
7
6
5
4
3
2
1
0
Field
SDAD[7:0]
Attribute
R/W
Initial Value
0x00
On detecting the writing, this register outputs the value saved in the register for one cycle. For this period,
n MADATA[15:0] holds the prior values. For the external bus interface, the power-on sequence of SDRAM
is automatically executed, so usually this register is not used. Only for the settings in operation (extended
mode register setting etc.), this register is used.
When setting SDCK=0, the mode is entered into the power down mode immediately. In this case, the
state of PDON bit of SDRAM mode register has no relation with this operation. The mode is returned by
an access to SDRAM. Refresh, or, writing to this register. To stop the refresh operation, set ROFF=1
(Refresh OFF).
[bit31]PEND: Pend
Immediately after detecting the writing to this register, this bit is asserted because the operation cannot be
executed instantly due to an access to a different device. Before writing this register, check this bit and
confirm that the bit is deasserted. When this bit is written during assertion, the operation is not
guaranteed.
bit
Description
0
Writing to SDCMD register is enabled.
1
Writing to SDCMD register is disabled.
[bit30:21] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.