Cypress FM4 Series - Error Status Register (EST)

CHAPTER 14: External Bus Interface
836 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
6.12 Error Status Register (EST)
The following shows the configuration of EST.
bit
31
30
29
28
27
26
25
24
Field
Reserved
Attribute
-
Initial Value
-
bit
23
22
21
20
19
18
17
16
Field
Reserved
Attribute
-
Initial Value
-
bit
15
14
13
12
11
10
9
8
Field
Reserved
Attribute
-
Initial Value
-
bit
7
6
5
4
3
2
1
0
Field
Reserved
WERR
Attribute
-
R
Initial Value
-
0
[bit31:1] Reserved: Reserved bits
The read value is undefined.
Set this bit to 0 when writing.
[bit0] WERR
This bit is used to indicate the reception of error response in a write access when the continuous write
access of Access Mode Register (AMODE) is enabled (WAEN=1). On the reception of error response,
this bit is changed from 0 to 1. When an error response is received in the subsequent write access, the bit
is rewritten to a new state.
To clear this register to be initial state, write 0 to WERRCLR bit of Error Status Clear Register (ESCLR).
When the continuous write access of Access Mode Register (AMODE) is enabled (WAEN=0) and the
frequency division ratio of Division Clock Register (DCLKR) is one (MDIV=0), the state of this bit is not
held in write access.
bit
Description
0
No error response exists.
1
Error response exists.