Cypress FM4 Series - PLL Control Register 1 (PLL_CTL1)

CHAPTER 2-1: Clock
70 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.11 PLL Control Register 1 (PLL_CTL1)
The PLL_CTL1 sets the PLL frequency division ratio.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
PLLK
PLLM
Attribute
R/W
R/W
Initial value
0000
0000
Register functions
[bit7:4] PLLK: PLL input clock frequency division ratio setting bits
bit 7:4
Description
0000
The frequency division is (PLLK value +1). (Frequency division : 1 to 16)
Example: PLLK value (0000) +1 => 1/1 frequency [Initial value]
0001
-
-
1111
[bit3:0] PLLM: PLL VCO clock frequency division ratio setting bits
bit3:0
Description
0000
The frequency division is (PLLM value +1). (Frequency division : 1 to 16)
Example: PLLM value (0000) +1 => 1/1 frequency [Initial value]
0001
-
-
1111
Notes:
− Set each frequency division ratio before enabling the PLL oscillation enable bit (PLLE) of the
SCM_CTL register.
− This register is not initialized by software reset.