Cypress FM4 Series - Hwintclr[N] Register

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 569
5.10 HWINTCLR[n] Register
The HWINTCLR[n] Register is a register for clearing the HWINT[n] Register.
Register configuration
Address
+0x50
Field
HWINTCLR[31:0]
+0x54
Field
HWINTCLR[63:32]
+0x58
Field
HWINTCLR[95:64]
+0x5C
Field
HWINTCLR[127:96]
+0x60
Field
HWINTCLR[159:128]
+0x64
Field
HWINTCLR[191:160]
+0x68
Field
HWINTCLR[223:192]
+0x6C
Field
HWINTCLR[255:224]
Attribute
(applicable to all areas)
W
Initial value
(applicable to all areas)
0x0000000000000000
Register function
The HWINTCLR[n] Register is a write-only register for clearing the HWINT[n] Register from the CPU.
When the DSTC is not in the normal state, no write access can be made to this register.
Writing "1" to this register can clear the HWINT[n] Register to "0". Writing "0" to this register is ignored.
The read value is always "0".
bit[255:0] HWINTCLR[255:0] (Hardware transfer interrupt clear)
Access
Function
Writing "0"
Causes no operation to be executed.
Writing "1"
Clears the HWINT[n] Register to "0".
Reading
All bits in this register always read "0".
If the DSTC installed in a product supports HW-128 channels, the HWINTCLR[255:128] bits are a
reserved area whose value is fixed at "0".
If the DSTC installed in a product supports HW-64 channels, the HWINTCLR[255:64] bits are a reserved
area whose value is fixed at "0".