Cypress FM4 Series - CRC Computing Configuration Register

CHAPTER 19: Programmable CRC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 945
4.5 CRC Computing Configuration Register
The CRC computing configuration register (PRGCRC_CFG) sets the operation functions of
programmable CRC and reads the state.
Register configuration
Address: +0x0C
Bit
31
30
29
28
27
26
25
24
Field
Reserved
Reserved
Reserved
LOCK
Reserved
CDEN
CIEN
CIRQ
Attribute
R
R
R
R
R
R/W
R/W
R
Initial value
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Field
SZ[1:0]
TEST [5:0]
Attribute
R/W
R/W
Initial value
1
1
1
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Field
Reserved
Reserved
Reserved
Reserved
FI[1:0]
FO[1:0]
Attribute
R
R
R
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CIRQCLR
Attribute
R
R
R
R
R
R
R
W
Initial value
0
0
0
0
0
0
0
0
Register functions
[bit0] CIRQCLR (RGCRC Interrupt request Clear)
Access
Application
Write 0
No effect in operation.
Write 1
Clears the CIRQ register to 0.
Read
Always reads 0.
The CIRQCLR clears the CIRQ register to "0". By clearing the CIRQ register to "0", the interrupt signal
from programmable CRC can be negated. Write access to this register is not allowed when CRC
computing is performed (PRGCRC_CFG.LOCK="1") and note that the CIRQ register is not cleared to "0".
[bit7:1] Reserved bits
Writing has no effect in operation. Read value is always "0".