Cypress FM4 Series - System Clock Mode Control Register (SCM_CTL)

CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 59
5.1 System Clock Mode Control Register (SCM_CTL)
The SCM_CTL selects the master clock and enables/disables the clock oscillation.
Register configuration
bit
7
6
5
4
3
2
1
0
Field
RCS[2:0]
PLLE
SOSCE
Reserved
MOSCE
Reserved
Attribute
R/W
R/W
R/W
-
R/W
-
Initial value
000
0
0
-
0
-
Register functions
[bit7:5] RCS[2:0]: Master clock switch control bits
bit7
bit6
bit5
Description
0
0
0
High-speed CR clock [Initial value]
0
0
1
Main clock
0
1
0
Main PLL clock
0
1
1
Setting is prohibited
1
0
0
Low-speed CR clock
1
0
1
Sub clock
1
1
0
Setting is prohibited
1
1
1
Setting is prohibited
[bit4] PLLE: PLL oscillation enable bit
bit
Description
0
Disables PLL oscillation [Initial value]
1
Enables PLL oscillation
[bit3] SOSCE: Sub clock oscillation enable bit
bit
Description
0
Disables sub clock oscillation [Initial value]
1
Enables sub clock oscillation
[bit2] Reserved: Reserved bit
"0" is read from this bit.
Set this bit to 0 when writing.
[bit1] MOSCE: Main clock oscillation enable bit
bit
Description
0
Disables main clock oscillation [Initial value]
1
Enables main clock oscillation
[bit0] Reserved: Reserved bit
0 is read from this bit.
Set this bit to 0 when writing.