CHAPTER 8: Interrupts
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 403
4.16 IRQ039/040/041/042/043/044/045/046/098/099/100/101 Batch Read
Register (IRQxxxMON)
The IRQ039MON to IRQ046MON Registers can read out at once the interrupts (interrupts of base timer
ch.0 to ch.7) assigned to exception no. 55 to no. 62 respectively.
The IRQ098MON to IRQ101MON Registers can read out at once the interrupts (interrupts of base timer
ch.8 to ch.11, GDC) assigned to exception no. 114 to no. 117 respectively.
Register configuration
Register function
[bit31:9] Reserved: Reserved bits
A reserved bit reads 0.
[bit8] GDCINT
Register by has the following features. Other than the following becomes a reserved bit 0 is read.
There is no interrupt request of the GDC Signature0.
An interrupt request of the GDC Signature0 has been made.
There is no interrupt request of the GDC Display0_Sync0.
An interrupt request of the GDC Display0_Sync0 has been made.
There is no interrupt request of the GDC Display0_Sync1.
An interrupt request of the GDC Display0_Sync1 has been made.
There is no interrupt request of the GDC ContentStream1.
An interrupt request of the GDC ContentStream1 has been made.
[bit7:2] Reserved: Reserved bits
A reserved bit reads 0.