CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 561
5.5 CFG Register
The CFG (configuration) Register sets operation functions of the DSTC.
Register configuration
Register function
The CFG (configuration) Register sets operation functions of the DSTC. Use an 8-bit (byte) access to
write a value to this register. The 16-bit write access and 32-bit write access to this register are ignored.
When the DSTC is in the normal state, no write access can be made to this register.
bit[8] SWINTE (Software interrupt enable)
Disables the SWINT interrupt. (Initial value)
If SWTR:SWST has been set to "1", the DSTC does not generate the SWINT interrupt.
Enables the SWINT interrupt.
If SWTR:SWST has been set to "1", the DSTC generates the SWINT interrupt.
A read access to this bit reads the value of this bit.
bit[9] ERINTE (Error interrupt enable)
Disables the ERINT interrupt. (Initial value)
If MONERS:EST has been set to "001", "010", "100" or "101",
the DSTC does not generate the ERINT interrupt.
Enables the ERINT interrupt.
If MONERS:EST has been set to "001", "010", "100" or "101",
the DSTC generates the ERINT interrupt.
A read access to this bit reads the value of this bit.
MONERS:EST=”011” is transfer compulsory stop error by standby transition command. In this case,
ERINT interrupt is not asserted. For details, see "3.2.9 Standby Function"
bit[10] RBDIS (Read skip buffer disable)
Enables the read skip buffer function of the DES. (Initial value)
The HWDESP[n] reference skip function of HWDESPBUF is enabled.
Disables the read skip buffer function.
The HWDESP[n] reference skip function of HWDESPBUF is disabled.
A read access to this bit reads the value of this bit.
If the RBDIS bit is set to "0", the read skip buffer function and HWDESPBUF function shown in Figure 3-5
are enabled. Accordingly, the DSTC skips referring to the DES and HWDESP[n] Register on the memory
and, in turn, the processing speed of the DSTC increases. Nonetheless, the DSTC may not be able to
recognize a change in the value of DV of DES0 by the CPU or the modification of the value of the
HWDESP[n] Register. Therefore, if the value of DV of DES0 has been changed or the value of the