CHAPTER 2-1: Clock
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 45
3.2 Internal Bus Clock Frequency Division Control
This section explains the internal bus clock frequency division.
Frequency division ratio from the base clock can be set independently for each internal bus clock.
This function can set the operating frequency optimized for each circuit.
The maximum frequency of the internal bus clock differs by product. For details, see Data Sheet of the
product used.
To set the frequency division ratio of internal bus clocks, use the Base Clock Prescaler Register
(BSC_PSR), APB0 Prescaler Register (APBC0_PSR), APB1 Prescaler Register (APBC1_PSR), APB2
Prescaler Register (APBC2_PSR), and Trace Clock Prescaler Register (TTC_PSR). For details on each
register, see 5. List of Clock Generation Unit Registers.
Setting the Bus Clock Frequency Division
The set frequency division ratio is not cleared by a software reset. The latest value is retained before
the software reset.
The value is initialized by a reset other than software resets.
Before changing the initially set master clock to a faster source clock, be sure to set the frequency
division ratio.
If a combined value of master clock, PLL multiplication, and frequency division ratio settings exceeds
the maximum operating frequency of each internal bus, the operation corresponding to the setting is not
guaranteed.
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