CHAPTER 6: Low Power Consumption Mode
212 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.4 Operations in Stop Mode
In Stop mode, all oscillators stop. All functions stop operating except for the Low Voltage Detection
Circuit.
Functions of Stop Mode
CPU and on-chip memory
In STOP mode, the CPU clock supplied to the CPU, and the AHB bus clock supplied to the on-chip
memory and the DMA controller stop. However, data in the on-chip memory is retained. In addition, the
debug function stops.
Peripherals
In STOP mode, all APB bus clocks stop. Except for the Low Voltage Detection Circuit, all resources stop
at their respective states they were in immediately before the CPU transits to STOP mode.
Oscillator clocks
All oscillator clocks stop.
Resets and interrupts
Resets and interrupts can be used for returning from STOP mode.
External bus
The external bus stops in STOP mode.
Pin state
The SPL bit in the Standby Mode Control Register (STB_CTL) can control whether an external pin stays
at the state it was in immediately before the CPU transits to STOP mode or changes to high impedance
state.
Procedure for Setting STOP Mode
Execute the following procedure to make the CPU transit to STOP mode.
1. Write 0 to the RTCE bit in the RTC Mode Control Register (PMD_CTL).
2. Write 0x1ACC, 0 and 0b10 to the KEY bits, DTSM bit and STM bits in the Standby Mode Control
Register (STB_CTL) respectively. Set the state of each pin in STOP mode by using the SPL bit
3. Write 1 to the SLEEPDEEP bit in the Cortex-M4F System Control Register.
4. Execute the WFI instruction or the WFE instruction.
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