CHAPTER 7-3: VBAT Domain(B)
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 303
2.1 Interfacing with Always-on Domain
This section explains the methods of interfacing the VBAT Domain withe the Always-on Domain.
Overview of Interfacing
The VBAT Domain is driven by the 32 kHz oscillation circuit or a clock divided from PCLK.
Therefore, if an internal bus is directly connected to a register belonging to the VBAT Domain, a bus
master such as the CPU is made to wait when accessing such register.
The FM4 Family has the following two mechanisms to prevent an access from being made to wait.
− A buffer is built in the Always-on Domain. An access from an internal bus is directed to that buffer.
− Data is transferred between the buffer of the Always-on Domain and the register of the VBAT
Domain.
In the documents of the FM4 Family, data transfer operations between the buffer of the Always-on
Domain and the register of the VBAT Domain are called as stated below.
− Recall: data transfer from the register of the VBAT Domain to the buffer of the Always-on Domain
− Save: data transfer from the buffer of the Always-on Domain to the register of the VBAT Domain
Since data written to the buffer is erased if the VCC power supply is off, save the data in the register of
the VBAT Domain while the VCC power supply is on.
Immediately after the VCC power is turned on or when a reset occurs in the Always ON domain, the
buffer value is initialized by an Always ON domain reset signal.
Therefore, before reading data from the buffer, execute a recall operation to restore data retained in the
register while the VBAT power supply (backup power supply) was on to the buffer.
The calendar data of the RTC in the buffer is not automatically updated.
Before reading the time data from the buffer, execute the recall operation to transfer the time data saved
in the register of the VBAT Domain to the buffer.
To Next Page
Loading...
