Cypress FM4 Series - Hwdesp[N] Register

CHAPTER 11: DSTC
FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E 559
5.3 HWDESP[n] Register
The HWDESP[n] (Hardware DES pointer) Register sets the DESP of the DES that the DSTC refers to at
a transfer request of HW channel n.
Register configuration
Address: +0x04
bit
31
30
29
16
15
8
7
0
Field
Reserved
HWDESP[13:0]
Reserved
CHANNEL[7:0]
Attribute
R
R
R/W
R
R/W
Initial value
0
0
XXXXXXXXXXXX00
00000000
00000000
Register function
Set the HWDESP[n] Register before making an HW transfer request. This register can be accessed only
when the DSTC is in the normal state. Settings of an unused HW channel n are not necessary.
The number of the HWDESP[n] Registers corresponds to the number of HW channels. However, there is
only one register window that can be seen from the CPU. Access this register as explained below.
− To read the value of the HWDESP[n] Register from the CPU, use an 8-bit (byte) access to write to
CHANNEL[7:0] the channel number to be read first. Afterward, read the value of HWDESP[13:0]
with a 16-bit (halfword) access.
− To write the value of the HWDESP[n] Register from the CPU, use an 8-bit (byte) access to write to
CHANNEL[7:0] the channel number to be written first. Afterward, write a value to HWDESP[13:0]
with a 16-bit (halfword) access. If the write access is a 32-bit (word) access, writing a value to
CHANNEL[7:0] and writing a value to HWDESP[13:0] can be executed simultaneously.
The DSTC stores the DESP value of the HWDESP[n] Register in HWDESPBUF in Figure 3-5 before
using it. If HW Start requests of channel n are made successively, the DSTC uses the DESP value stored
in HWDESPBUF, but not the DESP value of the HWDESP[n] Register. Therefore, if the values of the
HWDESP[n] Register are modified via the CPU, invalidate the value stored in HWDESPBUF. The DESP
value of HWDESPBUF can be invalidated by modifying the value of the RBDIS bit in the CFG Register.
For details of the CFG Register, see "5.5 CFG Register".
bit[7:0] CHANNEL[7:0]
Access
Function
Writing
A write access to these bits sets the channel number (n) for the HWDESP[n] to which a read access
or a write access is made.
Reading
A read access to these bits reads the value of these bits.
If the DSTC with which a product equipped supports HW-128 channels, always write "0" to CHANNEL[7].
If the DSTC with which a product equipped supports HW-64 channels, always write "00" to
CHANNEL[7:6].
bit[29:16] HWDESP[13:0]
Access
Function
Writing
A write access to these bits writes the channel number of HWDESP[n] specified in CHANNEL[7:0].
Reading
A read access to these bits reads the channel number of HWDESP[n] specified in CHANNEL[7:0].
Align DES to the word boundary. Always write "00" to the lower 2 bits in the HWDESP Register. HWDESP
cannot be set to a value larger than "0x3FF0".