Cypress FM4 Series - Configuration a Register (DMACA)

CHAPTER 10: DMAC
494 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
5.3 Configuration A Register (DMACA)
This section explains configuration A register (DMACA).
bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Field
EB
PB
ST
IS[5:0]
Reserved
BC[3:0]
Attribute
R/W
R/W
R/W
R/W
-
R/W
Initial Value
0
0
0
000000
-
0000
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
TC[15:0]
Attribute
R/W
Initial Value
0x0000
[bit31] EB : Enable bit (individual-channel operation enable bit)
This bit controls the enabling and disabling of the transfer operation of an individual channel.
When this bit is set to "1", the relevant channel is enabled to operate and waits for a trigger to start its
transfer operation (the DMACR:DE must be set to "1").
If the EM bit (DMACB[0]) is not set to "1", DMAC clears this bit to "0" upon the completion of the transfer.
When this bit is set to "0", the relevant channel is disabled to operate and does not perform transfer
operation until it is set to "1". Also, if it is in the middle of transfer operation, it is forced to stop the transfer.
This bit can be used to force the relevant channel that is currently in transfer operation to stop it and reset
the configuration register.
bit
Function
0
The operation of the relevant channel is disabled. (Initial value)
1
The operation of the relevant channel is enabled.
[bit30] PB : Pause bit (individual-channel pause bit)
This bit controls the pause/cancellation of the transfer operation of an individual channel.
When this bit is set to "1" and the relevant channel is currently in transfer operation, it puts the transfer on
pause. When this bit is set to "0", it resumes the transfer.
This bit is cleared to "0", when the transfer operation of the channel is completed.
Even if a transfer request from an external/peripheral device is asserted, the channels in Pause state
ignore the transfer request. In the cases of Block transfer and Burst transfer, the relevant channel does
not start a transfer, even if the pause is cleared. In order to complete a transfer when a pause is set
during the transfer, an additional transfer request is required after the pause is cancelled.
This bit can be used to put a transfer on pause without resetting the configuration register of the relevant
channel.
bit
Function
0
Cancels the pause of the transfer of the relevant channel.
1
Puts the transfer of the relevant channel on pause.
Note:
− In this case of setting this bit during DMACB.RC=”1”, DMACA.BC and DMACA.TC must be set to
reload value along with this bit by word access.