Cypress FM4 Series - PLL Clock Control

CHAPTER 2-1: Clock
46 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E
3.3 PLL Clock Control
This section explains the PLL clock control.
The PLL Clock Control Circuit is used to generate the main PLL clock from the main clock or high-speed
CR clock. The PLL Oscillation Circuit can enable/disable operation (oscillation), select the input clock, set
the stabilization wait time, and set the multiplication.
PLL Operation
The following explains operation of the main PLL clock.
− Configure the following settings using the PLL Clock Oscillation Stabilization Wait Time Setup
Register (PSW_TMR).
− Selecting the PLL input clock
− Setting the main PLL clock stabilization wait time
− The PLL oscillation enable bit (PLLE) of the System Clock Mode Control Register (SCM_CTL) must
be enabled to let the PLL Circuit start oscillating.
− When the PLL clock stabilization wait time has elapsed, and the "PLL oscillation stable bit" of the
System Clock Mode Status Register (SCM_STR) indicates a stable state, the preparation for
transition to main PLL clock mode completes.
− Master clock switch control bit (RCS[2:0]) of the System Clock Mode Control Register (SCM_CTL)
must be set to main PLL clock mode (RCS[2:0]=010) to change to main PLL clock mode.
Setting the Main PLL Clock Oscillation Stabilization Wait Time
The details are given in 5.10 PLL Clock Stabilization Wait Time Setup Register (PSW_TMR).
Notes:
− For block diagram of the PLL Clock Control Circuit, see 2. Clock Generation Unit
Configuration/Block Diagram.
− For the order of frequency division settings for each internal bus clock, see 4 Clock Setup
Procedure Examples.
− For the oscillation stabilization wait time, see 3.4 Oscillation Stabilization Wait Time.
− When selecting high-speed CR in the input clock of PLL, see 1. Notes when high-speed CR is
used for the master clock in B. List of Notes of Appendixes.
Setting the Multiplication Ratio to Generate the Main PLL Clock
Each frequency division clock in the PLL Multiplication Circuit must be set using PLL Control Register 1
(PLL_CTL1) and PLL Control Register 2 (PLL_CTL2). The following Table 3-1 provides example of
frequency division settings.